Experience

Experience Image

Research Scientist

Boston University, Boston, MA

Leading the digital research team for architectural design of a soft-output iterative decoder to improve the decoding performance for long codes constructed with short, high-rate codes.

May 2025 - Present
Experience Image

Postdoctoral Associate

Boston University, Boston, MA

Co-Led the development of an integrated unified decoder-demapper chip, designed in 40nm CMOS, to significantly enhance decoding performance by leveraging noise correlations—achieving lower power consumption, reduced area, and improved energy efficiency compared to state-of-the-art decoders.

Supervised and mentored a multidisciplinary team of Ph.D., M.S., and undergraduate students.

May 2024 - April 2025
Experience Image

Graduate Research Assistant

Boston University, Boston, MA

Led the development of the first integrated universal soft-detection decoder chip using ORBGRAND, achieving orders-of-magnitude reductions in energy and power consumption compared to state-of-the-art decoders — all within a compact 0.4 mm2 footprint, fabricated in 40nm CMOS.

Contributed to the development of the first integrated universal hard-detection decoder using GRAND. Demonstrated, for the first time, hard-detection decoding of CA-Polar codes, Random Linear Codes, and error correction for CRC codes.

Sep 2019 - April 2024
Experience Image

Research Intern

Qualcomm Technologies Inc., San Diego, CA

Designed and implemented a Python-based algorithm for detection and elimination of redundant and unused logic in Verilog RTL, streamlining digital module optimization before synthesis. The solution effectively reduced non-recurring engineering (NRE) efforts and improved power, performance, and area (PPA) metrics. Validated the algorithm on production-level IP from Qualcomm.

May 2023 - Aug 2023
Experience Image

Visiting Scholar

Massachusetts Institute of Technology, Cambridge, MA

Contributed to the development of a highly miniaturized ingestible electronic capsule for ultra-low-power sensing of bioluminescence to detect in-vivo diseases. Fabricated in 65nm CMOS, the capsule offers 2x higher resolution than state-of-the-art solutions.

Sep 2019 - June 2020
Experience Image

Research Assistant

Lahore University of Management Sciences, Lahore

Developed single-cell, multi-band rectifiers operating at millimeter-wave frequencies to harvest RF energy from the ambient environment for next-generation wireless sensors nodes and wireless power transfer applications.

June 2018 - Aug 2019

Education

Education Image

Boston University

Boston, MA
Ph.D. Electrical Engineering
Thesis: Energy-efficient custom integrated circuit design of universal decoders using noise-centric GRAND algorithms [Advisor: Rabia Yazicigil]
(Embargo Date: 05/23/2026)
May 2024
Education Image

Boston University

Boston, MA
M.Sc. Electrical Engineering

CGPA: 4.00/4.00

May 2021
Education Image

National Univeristy of Sciences and Technology

Islamabad, Pakistan
B.Sc. Electrical Engineering

CGPA: 3.87/4.00

June 2018

Skills

Technology

  • RTL Design and Verification
  • Custom ASIC Design
  • Physical chip design/PnR
  • Static Timing Analysis (STA)/ Primetime
  • Cadence (Innovus, Genus, Virtuoso)
  • DRC/LVS verification
  • FPGA/ Vivado
  • PCB Design and Testing
  • Software Defined Radio (SDR)
  • GNU Radio/ RF-NoC
  • DSP Architectures
  • Wireless Communication Systems

Programming

  • Verilog
  • System Verilog
  • C/C++
  • MATLAB
  • Python
  • Tcl
  • Assembly

More About Me